Packet Digital has a team of skilled ASIC design engineers and industry leading EDA tools. The team has successfully completed many FPGA-based projects. These designs have been taken from requirements capture to customer delivered RTL with tight timelines. Packet Digital's design methodology includes extensive testbench development and simulation verification to ensure confidence in the initial product.
FPGA and CPLD Development
- Clean, well documented Verilog and VHDL RTL
- Altera Quartus II and Xilinx Vivado/ISE design tools
- Experience with devices from Altera and Xilinx
- Timing, area, power analysis
Contact Us about your FPGA project!